1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and specially, the present invention relates to a semiconductor device in which an LDD (Lightly Doped Drain) is formed in a self-aligning manner and a manufacturing method thereof.
2. Description of the Related Art
Recently, in the field of an image display device, the development of a system-on-panel incorporating logical circuits such as a memory circuit and a clock generating circuit, besides a pixel, a driver circuit and the like, on a glass substrate has attracted attention. The technical development of manufacturing a TFT with high switching speed on a glass substrate is required to realize high-speed operation for driver circuit and logical circuit. A TFT with high switching speed is manufactured by using a semiconductor film with fewer crystal defects and by miniaturizing an element size.
Even if an element size is miniaturized proportionally, drive voltage cannot always be reduced proportionally in order to keep signal speed and response speed. Consequently, the vicinity of a drain region becomes high field by miniaturizing an element size of a MOS transistor. Accordingly, an electron and a hole having high energy, which are referred to as hot carriers are generated and caught in a gate insulating film. And it is known that this will cause a degradation phenomenon such as a fluctuation of threshold level.
It is effective to apply an LDD (Lightly Doped Drain) structure as an element structure. The LDD structure is formed by providing a low concentration impurity region (hereafter referred to as an LDD) in a drain end which is contact with a channel. As low concentration impurities, an n-type impurity is used in the case of an n-channel element and a p-type impurity is used in the case of a p-channel element. In this manner, electric field in the vicinity of the drain region is relieved and the occurrence of hot carriers is controlled by making gradient impurity concentration in the channel-drain junction. (For example, Reference. 1, S. Kishino “Novel fundamental of semiconductor device” Ohmsha, LTD. 1995. P201–207)
A degradation phenomenon caused by hot carriers is generated not only in a MOS transistor but also in a TFT. But it can also be prevented by applying an LDD structure as an element structure of a TFT as well as a MOS transistor.
The formation method of a general LDD structure in MOS transistor is explained with reference to FIGS. 1A to 1D, but the process to element separation and the process after the formation of an LDD are omitted here.
A gate insulating film 103 is formed on a semiconductor film 102 which has an isolated element. Next, a gate electrode 104 formed of polysilicon is formed on the gate insulating film 103. After fabricating the gate electrode 104 into a desired shape, ions at low concentration are doped into the semiconductor film 102. Next, a silicon oxide film 105 which is excellent in isotropic step coverage is formed on the gate electrode 104. Then, sidewalls 106 is formed by performing anisotropic etching in vertical direction to leave the silicon oxide 105 only on the sidewalls of the gate electrode. A source (or a drain) 108 is formed by doping ions at high concentration in the semiconductor film 102 so that ions do not penetrate the sidewalls 106. The ions at high concentration are not doped into the lower portion of the sidewalls 106, and then the lower portion of the sidewalls 106 is to be LDDs 107.
As described above, an LDD is formed in a self-aligning manner without patterning by using a sidewall. With miniaturization in an element size, there is a case in which the process in the scope of exceeding alignment accuracy of patterning is required. In this case, an LDD can be formed with higher precision in a self-aligning manner which does not involve patterning. Hence, the above method is used when alignment accuracy is higher in the case of using a self-aligning manner in the formation of an LDD.
An LDD can be formed in a TFT in the same way as a MOS transistor. An insulating material such as a glass substrate is used for forming a TFT. Therefore, a TFT is easily charged, and easily suffered damage from plasma especially in anisotropic etching to form sidewalls. In the element suffered damage from plasma, electrical charge in a gate insulating film and energy level in an interface between a semiconductor layer and a gate insulating layer are generated, and, as a result, deterioration such as fluctuation of threshold level is caused. Such damage from plasma generated in the formation process of an LDD is resulted from the difficulty in discharging electric charge accumulated in a gate electrode of which surface area is reduced by processing into a desired shape, and results in considerable impact on an element characteristic. Therefore, the damage from plasma is increased due to the increased charge density which is to be accumulated in the gate electrode as decreasing the surface area of the gate electrode by miniaturization of an element size, and as decreasing the thickness of the gate insulating film.
However, the miniaturization of an element size is required more and more to manufacture a TFT with high switching speed which is fundamental to an element for logical operation circuit, and to obtain higher integration. Additionally, it is difficult to repair the damage from heat treatment since a substrate made from a glass substrate which does not withstand very high temperature is used for low manufacturing cost. Consequently, the development of manufacturing method of a TFT having an LDD structure, which can take advantage of self aligning manner having high manufacturing accuracy and decrease the damage from the plasma as much as possible is needed.